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Monday, September 23 • 1:30pm - 5:00pm
PDC15: Tolerance Mistaken: Impacts of Not Properly Addressing Limitations of Material, Industry Standards and Assembly Process Limitations

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PDC15: Tolerance Mistaken: Impacts of Not Properly Addressing Limitations of Material, Industry Standards and Assembly Process Limitations

*Dale Lee, Plexus Corp.
Monday, September 23| 1:30pm — 5:00pm

Course Objectives
Electronic assemblies today are smaller, lighter with increased functionality per unit area and/or volume. The rate of new technology adoption is increasing through develop ever smaller packages with finer lead spacing and substrates with finer lines and spaces. However, design methods, industry standards, materials and manufacturing processes utilized during the product development and production process have not progressed to meet these new demands and thus many of the tolerance margins that were considered insignificant and acceptable in the past are now critical to high yield, reliable products. This presentation will highlight issues with today’s electronic designs and impacts when material limitations, industry standards and assembly tolerances are not adequately address during design, PCB fabrication, assembly and test.

Topics Covered
1. Industry Standards Limitations (IPC/JEDEC)
2. Component Package Technology A. New Packaging Technologies B. Units of Measure (Metric vs Imperial) C. Land Pattern Design
3. PCB Design
A. Laminate Limitations
B. Via hole Closure
C. Copper Etching Effects (pad/trace size)
D. Solder Mask Design
4. Leadless Component Packages (DFN, QFN, LGA, Chip)
A. Solder Mask/Silk Screen
B. Thermal balance
C. Thermal expansion/shrinkage
5. Assembly Technology
A. Material compatibility
B. Tolerances - Assembly/Tooling
C. Clean/No-clean

Monday September 23, 2019 1:30pm - 5:00pm CDT
Room 53

Attendees (4)