Course Objectives Both uncased active and passive component elements are candidates for embedding but the process of selecting these components must be made early in the design process. Developers have realized that in addition to passive components, embedding one or more active die elements on an inner layer of the circuit in close proximity to pre-packaged semiconductor(s) mounted on the outer surface, electrical interface between components can be minimized, considerably improving functional performance. This closer coupling of key passive and active semiconductor elements will: • Significantly reduce inductance • Contribute to increasing signal speed • Lower overall power consumption
Some components are easy candidates for integrating into the substrate while others may involve more complex processes and will be difficult to rationalize. And although a majority of the discrete passive and active devices may remain mounted on the outer surfaces of the circuit board, embedding a majority of the resistor functions and one or more silicon-based semiconductor elements within the inner layers of the structure can enable greater utilization of the circuit boards outer surfaces. This half-day course furnishes a comprehensive introduction to IPC-7092, Design and Assembly Process Implementation for Embedded Components.
The material presented has been developed to better enable the product designer and manufacturing specialist to have a clear understanding of the principles for embedding components in an organic multilayer circuit board structure. The course will include design guidelines, material selection and termination methodology for embedding both ‘active and passive components including formed and placed resistor, capacitor and inductor elements. Process variations for embedding and interconnecting thinned semiconductor elements within the multi-layer PCB will be illustrated with examples of both core type and coreless substrate structures.
Topics Covered: 1. Industry drivers for embedded component technology 2. Economic benefits for embedding components • Comparing passive component variations 3. Formed passive component methodology 4. Discrete passive component selection criteria 5. Addressing key factors in planning for ECP 6. Preparation for embedding semiconductors 7. Issues and concerns related to component supply chain 8. Core and coreless embedded component structures 9. Base material selection for the ECP application 10. Embedded component substrate development 11. Land pattern and circuit routing recommendations 12. Component attachment processes 13. Embedded component assembly variations 14. Semiconductor interface variations 15. Qualifying embedded component PCB fabricators
Sunday September 22, 2019 8:30am - 9:30am CDT
Room 53
PDC08: Design and Assembly Process Challenges for Bottom Terminations Components (BTCs) such as QFN, DFN and MLF in Tin-Lead & Lead Free World
*Ray Prasad, Ray Prasad Consultancy Group Sunday, September 22 | 1:30pm — 5:00pm
Course Objectives Bottom Termination surface mount Components (BTCs) go by various names such as QFN, DFN, SON, LGA, MLP, and MLF, which utilize surface to surface interconnections. BTCs are like BGAs which also have hidden terminations, but they are also very different. BTCs do not have spheres but rather metallized terminations or pads underneath the package. This minor difference in the physical I/O shape makes all the difference in design, assembly and rework between BTCs and BGAs.
Since there are no leads or balls in BTCs to take up any slack from package or board warpage, you essentially need perfection in design and assembly process. When was the last time you saw every thing perfect on any manufacturing floor?
One must also keep in mind that these parts are not the only components that must be mounted on the board. Look at any board. It will have other packages such as BGAs, fine pitch and even some through-hole components; and those components have their own unique design and assembly implementation requirements. So designing for BTCs may involve trial and error and lot of frustration by many companies. Additional frustration is caused by fast-paced changes in packaging technologies and the advent of Lead Free has compounded the designer’s task.
When it comes to inspection, BTCs pose even more challenge than BGAs. What you may see in visual inspection may look bad but may really be acceptable. And what you don’t or can’t see may really be critical. And the fact that the Process Engineer must worry about both too much solder and too little solder on the same BTC package makes the quality engineer nervous about field returns.
The objective of the course is to get away from the trial and error approach and provide you successful design and process practices commonly used by the industry. This course will cover the practical details of BTC design and assembly processes.
This course is based on Surface Mount Technology: Principles by Ray Prasad and Practice and IPC 7093 Design and Assembly Process Guidelines for BTCs also co-chaired Ray. This course identifies many of the characteristics that influence the successful implementation of robust and reliable BTC assembly processes.
This is not a theoretical course. It s based on Mr. Prasad's over two decades of experience at Boeing, Intel and numerous clients and deals with "real-world" problems in lead free and tin-lead BTC implementation.
Topics Covered 1. Introduction 1.1. Pros and Cons of BTC 1.2. Pull Back Vs Non Pull Back 1.3. BTC Package Manufacturing Process 2. Major Design Considerations for BTCs 2.1. Laminates and Surface Finish Considerations 2.2. Land Pattern and Stencil Design Guidelines 2.3. Component considerations 3. Assembly Process Guidelines for BTC 3.1. Solder Paste Printing- the Key Process Step 3.2. Reflow Process Guidelines 3.3. BTC Solder Joint Quality Requirements 3.4. BTC Rework Process 4. Key strategies in design and manufacturing processes to prevent field returns
Sunday September 22, 2019 1:30pm - 5:00pm CDT
Room 53
Course Objectives This half-day workshop focuses on solder paste and how to select the best one for an operation using the new SMTA Miniaturization Test Vehicle. Solder pastes have over 20 individual characteristics that must be considered during the selection process. Moreover, some characteristics conflict with each other and the tradeoffs must be carefully considered when determining the best process chemistry in order to avoid surprises on the production line. Many operations delay updating their soldering materials because of the high cost, lost production time, and complexity of the materials. These concerns have been met with a low-cost evaluation kit that minimizes line time, maximizes test efficiency, and demonstrates the tradeoffs in performance characteristics. The kit includes pre-designed PCB boards and components; an active spreadsheet to configure the PCB population, cost and sample sizes; stencil and vacuum board support designs; ODB++ database; placement files; SPI files; step-by-step directions for a 30-print DOE; an SMT soldering reference manual; directions for statistical reduction; and the customizable Score Card, which helps assemblers understand the tradeoffs involved and chose the best possible product. The hardware for the kit is available for purchase from commercial suppliers; the documentation and user files are available for FREE download from a website. This course discusses each characteristic of solder paste, how it impacts the SMT process, how the kit tests it, and how and why the board was designed. The Score Card is the key to customizing the test to a specific operation. Attendees will be encouraged to consider the solder paste characteristics on the Score Card as it relates to their SMT operations in an open discussion forum.
Topics Covered 1. Kit Overview 2. Solder Paste Characteristics 2.1. Categories and details 3. PCB Design 3.1. Top Side Elements 3.2. Bottom Side Elements 4. Components 4.1. Size Range 4.2. Cost Range 4.3. Bill of Materials Configurator Spreadsheet 5. Nesting the Tests for Efficiency 5.1. One side sits for abandon test while the other side gets worked in a shear test 6. Test Execution Order 6.1. Top Side 6.2. Bottom Side 6.3. Bottom Side 6.4. Top Side 7. Data Collection and Reduction 7.1. Print 7.2. Reflow 8. Score Card 8.1. Weighting each factor on importance to the specific operation and open discussion 8.2. Ranking each paste’s performance relative to each other 8.3. Category subtotals - Tradeoffs 8.4. Overall score 9. Fatal Flaws 9.1. Graping 9.2. Voiding 9.3. Peaking 9.4. Wipe Sensitivity 9.5. Other 10. Other uses for the SMTA MTV 11. Q&A
Monday September 23, 2019 8:30am - 12:00pm CDT
Room 53
PDC15: Tolerance Mistaken: Impacts of Not Properly Addressing Limitations of Material, Industry Standards and Assembly Process Limitations
*Dale Lee, Plexus Corp. Monday, September 23| 1:30pm — 5:00pm
Course Objectives Electronic assemblies today are smaller, lighter with increased functionality per unit area and/or volume. The rate of new technology adoption is increasing through develop ever smaller packages with finer lead spacing and substrates with finer lines and spaces. However, design methods, industry standards, materials and manufacturing processes utilized during the product development and production process have not progressed to meet these new demands and thus many of the tolerance margins that were considered insignificant and acceptable in the past are now critical to high yield, reliable products. This presentation will highlight issues with today’s electronic designs and impacts when material limitations, industry standards and assembly tolerances are not adequately address during design, PCB fabrication, assembly and test.
Topics Covered 1. Industry Standards Limitations (IPC/JEDEC) 2. Component Package Technology A. New Packaging Technologies B. Units of Measure (Metric vs Imperial) C. Land Pattern Design 3. PCB Design A. Laminate Limitations B. Via hole Closure C. Copper Etching Effects (pad/trace size) D. Solder Mask Design 4. Leadless Component Packages (DFN, QFN, LGA, Chip) A. Solder Mask/Silk Screen B. Thermal balance C. Thermal expansion/shrinkage 5. Assembly Technology A. Material compatibility B. Tolerances - Assembly/Tooling C. Clean/No-clean
Monday September 23, 2019 1:30pm - 5:00pm CDT
Room 53
